The present invention relates to programmable devices, and more particularly relates to a structure for storing information for controlling operation of a device including a plurality of programmable cells.
A programmable device, typified by FPGA (Field Programmable Gate Array), includes a number of programmable cells which perform various operations, with each programmable cell carrying out a specific operation corresponding to the processing to be realized by the programmable device. Such a programmable device, in which a large number of programmable cells are simultaneously operated to execute enormous operations typified by multimedia processing, has been attracting much attention recently. Configuration information indicates what operation is to be executed by each programmable cell, and this configuration information is stored in an internal memory in each programmable cell.
In a known programmable device technique, all of the programmable cells have the same structure and include internal memories of the same structure (see U.S. Pat. No. 6,281,703).
In this known structure, however, every time the programmable device is powered on, configuration information must be stored in all of the programmable cells included in the programmable device. The known technique thus has a problem in that the amount of time required for the configuration (which will be hereinafter referred to as a “configuration time”) is increased.
Also, the above-described programmable device, in which all of the programmable cells have the same structure and include internal memories of the same structure, has another problem in that the internal memories occupy a large circuit area in the device.